According to a manufacturing method of the semiconductor device disclosed in JP-A-2001-144173 corresponding to U.S. Pat. No. 6,524,890 and U.S. Pat. No. 6,879,029, a wafer for forming elements is prepared, and trenches each having a predetermined depth from a main side of the wafer are formed firstly. Subsequently, the trenches are filled with an insulating layer, and then, the wafer is thinned by chemical mechanical polishing from a rear side of the wafer, so that the insulating layer is exposed. Thereby, the insulating layer penetrates the wafer and element formation regions can be isolated by the insulating layer.
In the above-mentioned manufacturing method, after the trenches each having the predetermined depth from the main side of the wafer is filled with the insulating layer, the wafer is thinned by chemical mechanical polishing from the rear side of the wafer. Thus, a surface including both a silicon substrate configuring the wafer and the insulating layer made of such as an oxide film needs to be polished. Therefore, stress due to polishing is concentrated at an interface between the silicon substrate and the insulating layer, and cracks may generate in the silicon substrate, for example. In addition, in case that the wafer is thinned by etching not polishing, structural steps may generate over the rear side of the wafer due to the difference of etching rate between the silicon substrate and the insulating layer.
Moreover, in case that the trenches are not filled sufficiently with the insulating layer, the element formation regions may separate from the wafer by force applied to the element formation regions while the wafer is thinned.